1. Technical Field of the Invention
The present invention relates to a semiconductor device having a dielectric capacitor, a manufacturing method for the same, and an electronic device using the same, and more specifically to a semiconductor device in which a dielectric capacitor is driven by an active element formed on an insulating substrate, a manufacturing method for the same, and an electronic device using the same.
2. Description of the Related Art
Recently, semiconductor devices for memories such as a nonvolatile memory (ferroelectric memory) using ferroelectric materials and a dynamic random access memory (DRAM) using high-dielectric materials have been actively studied, and a number of products of these have been supplied onto the market. Semiconductor devices of these ferroelectric memories and DRAMs have a switching transistor, a capacitor is connected to one diffusion layer (source region or drain region) of this switching transistor to form a memory cell, and charges are accumulated in this capacitor, whereby data is stored.
As a ferroelectric capacitor to be used as a ferroelectric memory uses ferroelectric materials such as PZT (PbZrxTi1-xO3), PLZT (Pb1-yLayZrxTi1-xO3), and SBT (SrBi2Ta2O9) as a capacitance insulating film, and by polarizing the ferroelectric materials, nonvolatile data can be stored. On the other hand, a high-dielectric capacitor to be used as a DRAM uses a high-dielectric thin film of BST (BaxSr1-xTiO) as a capacitance insulating film, and effective film thickness reduction has been promoted in accordance with required capacity increases.
For example, prior art 1 (Japanese Published Unexamined Patent Application No. 2002-334970) discloses a semiconductor device having a switching transistor and a capacitor. FIG. 13 is a sectional view of such a conventional semiconductor device. As shown in FIG. 13, in this semiconductor device, an MOS (Metal Oxide Semiconductor) type switching transistor 119 is provided on the surface of a silicon single crystal substrate 101, and a dielectric capacitor 118 is provided above this switching transistor 119 via interlayer dielectric films 105, 108, and 111. The source or drain of the switching transistor 119 is connected to a lower electrode 113 of the dielectric capacitor 118 by a multilayer metal interconnection structure including interconnections 107 and 110.
In the switching transistor 119, two diffusion layers 103 that serve as a source and a drain are formed on the surface of a silicon single crystal substrate 101 sectioned by oxide films 102, and above the channel region between the diffusion layers 103, a gate electrode 104 is formed via a gate insulating film 120. An interlayer dielectric film 105 is formed so as to cover this switching transistor 109, and metal interconnections 107 are formed thereon. The metal interconnections 107 are electrically connected to the two diffusion layers 103 of the switching transistor 119 by plugs 106. The metal interconnection 107 connected to one diffusion layer 103 is used as an interconnection for connecting the dielectric capacitor 118 and the switching transistor 119. The metal interconnection 107 connected to the other diffusion layer 103 is used as a bit line.
An interlayer dielectric film 108 is formed so as to cover the interlayer dielectric film 105 and the interconnection 107, and a metal interconnection 110 is formed thereon. Furthermore, an interlayer dielectric film 111 is formed so as to cover the interlayer dielectric film 108 and the interconnection 110, and on this interlayer dielectric film 111, a dielectric capacitor 118 is provided. In this dielectric capacitor 118, a lower electrode 113, a dielectric thin film 114, and an upper electrode 115 are laminated in order. The lower electrode 113 is electrically connected to the interconnection 110 via a via hole 112.
Furthermore, an interlayer dielectric film 116 is formed so as to cover the dielectric capacitor 118 and the interlayer dielectric film 111, and on this interlayer dielectric film 116, a metal interconnection 117 is provided. This metal interconnection 117 is provided so as to fill up a contact hole formed in the interlayer dielectric film 116, and is electrically connected to the upper electrode 115. The metal interconnection 117 is used as a plate interconnection.
In these lower electrode 113 and upper electrode 115, in order to prevent deterioration of intrinsic polarization of the dielectric thin film 114 due to deficiency of oxygen, a metal having a low affinity with oxygen such as Pt, Pd, Ir, Rh, Os, Au, Ag, or Ru, or a conductive oxide film of PtOx, PdOx, IrOx, RhOx, OsOx, AuOx, AgOx, or RuOx is used. At the interface between the lower electrode 113 and the via hole 112, in order to prevent relative reaction and relative diffusion of Pt or the like of the lower electrode 113 and W or the like of the via hole 112, a barrier layer (not shown) made of a conductive nitride film of TiN or the like is formed.
The dielectric thin film 114 is a ferroelectric thin film of BaTiO3, PbTiO3, PZT, PLZT, SBT, or the like or a high-dielectric thin film of BST etc. The dielectric thin film of these is formed on the lower electrode by means of sputtering, a sol-gel method, or a CVD (Chemical Vapor Deposition) method, and is crystallized into a perovskite-like structure by annealing at a predetermined temperature. The ferroelectric thin film thus formed has a polycrystalline structure. In this annealing, according to prior art 2 (Japanese Published Unexamined Patent Application No. H04-85878), it is preferable that heating is carried out in the atmosphere containing oxygen at 600° C., and one hour of annealing is necessary. In prior art 1, it is mentioned that the CVD method is used for film formation, crystallization is carried out by heating in the atmosphere of hydrogen to 300 to 500° C., and the surface of the film can be flattened by irradiation with an excimer laser.
In such a conventional semiconductor device, the structure below the lower electrode 113 of the memory cell is the same as that of an LSI (Large Scale Integrated Circuit) that has no capacitor. Therefore, this can be manufactured by a normal LSI manufacturing process by using an existing logic circuit.
However, as described above, this conventional semiconductor nonvolatile storage device is manufactured by the same LSI manufacturing process as that for a general existing logic circuit, so that the manufacturing costs are comparatively high although the storage capacity is comparatively easily increased.
On the other hand, it is expected that not only computers but also various electronic devices including televisions and other home electric appliances will be connected to the Internet in accordance with the advent of a ubiquitous society. Accordingly, the number of addresses of electronic devices on Internet (IP addresses) will be rapidly increase due to introduction of the Internet protocol IPv6. The increase in the number of IP addresses will lead to an increase in temporary (the period of use is much shorter than that of conventional electronic devices) or disposable electronic (recognition and storage) devices such as IC tags (wireless ID tags and radio-frequency ID tags, etc.) and IC cards. Most of these electronic devices have no power source, so that nonvolatile semiconductor devices using the above-described ferroelectric thin films or high-dielectric thin films are used for recognition and storage of data. In such temporary or disposable electronic devices, manufacturing of a semiconductor device having a proper storage capacity at very low cost is demanded more than realization of large capacity. However, it is difficult to meet this demand by the above-described conventional semiconductor devices.
On the other hand, as a transistor that is manufactured at low cost and replaced with the conventional switching transistor manufactured by the LSI manufacturing process, a thin film transistor is available in which a semiconductor layer is formed on an inexpensive substrate such as a low melting point substrate containing no alkali metal (alkali-free) and used as an active layer. As this thin film transistor, one using amorphous silicon or polysilicon (polycrystalline silicon) hydride as an active layer has been made practicable, however, in a nonvolatile semiconductor device, a polysilicon thin film having higher carrier mobility and higher drive performance has been used. In a thin film transistor using this polysilicon thin film, for example, as disclosed in prior art 3 (Japanese Published Unexamined Patent Application No. H09-116159) and prior art 4 (Japanese Published Unexamined Patent Application No. H10-242471), a polysilicon thin film serving as a source/drain and a channel is formed on an insulating substrate, a gate insulating film and a gate electrode are formed on this polysilicon thin film, and hydrogen plasma processing is applied, whereby the polysilicon thin film is activated by hydrogen passivation.
On the other hand, it is desirable that a semiconductor storage device is used together with a higher-function semiconductor device having an operation function. Conventionally, by forming a high-function element such as a CPU formed by the LSI process on a single crystal silicon substrate and a memory element into one chip, the packaging cost was reduced. Furthermore, for the memory element, the design rules were made more detailed and the memory capacity to be formed per unit area was increased, and as a result, the costs were reduced.
On the other hand, the polysilicon thin film of the thin film transistor is formed by, for example, the CVD method, and this CVD film contains many Si dangling bonds that do not rarely exist in a silicon single crystal substrate. Si dangling bonds are dangling bonds with Si—Si bonds cut, and are bonded to contaminant atoms and deteriorate the semiconductor performance. Therefore, it is necessary to eliminate such Si dangling bonds.
Therefore, for example, in prior art 3, Si dangling bonds are bonded to hydrogen by applying hydrogen plasma processing to a polysilicon film that serves as a source/drain region and a channel region formed on an insulating substrate to form Si—H bonds, whereby the dangling bonds are electrically inactivated.
However, the above-described conventional techniques have the following problems. When a switching transistor is formed by using the technique of prior art 2 and a dielectric capacitor is formed thereon, Si—H bonds are thermally unstable, and due to the heating process when forming a ferroelectric oxide film to be used for the dielectric capacitor, the Si—H bonds are cut and Si dangling bonds are generated again.
In addition, due to action of hydrogen contained in the polysilicon film as a reductant, oxygen deficiency occurs in the ferroelectric oxide film to be used for the dielectric capacitor, and this may result in lowering of the non-dielectric constant and an increase in leak current.